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CY8CLED04
EZ-ColorTM HB LED Controller
Features
HB LED Controller Configurable Dimmers Support up to 4 Independent LED Channels 8-32 Bits of Resolution per Channel Dynamic Reconfiguration Enables LED Controller plus other Features; CapSense, Battery Charging, Motor Control... Visual Embedded Design, PSoC Express LED Based Express Drivers * Binning Compensation * Temperature Feedback * DMX512

PrISM Modulation Technology Reduces Radiated EMI Reduces Low Frequency Blinking Advanced Peripherals (PSoC Blocks) 4 Digital PSoC Blocks Provide: * 8 to 32-Bit Timers, Counters, and PWMs * Up to 2 Full-Duplex UART * Multiple SPITM Masters or Slaves * Connectable to all GPIO Pins 6 Rail-to-Rail Analog PSoC Blocks Provide: * Up to 14-Bit ADCs * Up to 9-Bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators Complex Peripherals by Combining Blocks Capacitive Sensing Application Capability
Complete Development Tools Free Development Software * PSoC DesignerTM * PSoC ExpressTM Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128 KBytes Trace Memory Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIO Four 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Flexible On-Chip Memory 16K Flash Program Storage 50,000 Erase/Write Cycles 1K SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Full-Speed USB (12 Mbps) Four Uni-Directional Endpoints One Bi-Directional Control Endpoint USB 2.0 Compliant Dedicated 256 Byte Buffer No External Crystal Required
Cypress Semiconductor Corporation Document Number: 001-13108 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 13, 2007
CY8CLED04
Overview
Block Diagram
Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog
CPU Core (M8C) Clock Sources (Includes IMO and ILO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital 2 Decimator Clocks MACs Type 2
I2C
Internal POR and LVD Voltage System Resets Ref.
USB
Analog Input Muxing
SYSTEM RESOURCES
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EZ-Color Functional Overview
Cypress' EZ-Color family of devices offers the ideal control solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-ChipTM); with Cypress' PrISM (precise illumination signal modulation) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family support up to 16 independent LED channels with up to 32 bits of resolution per channel, enabling lighting designers the flexibility to choose the LED array size and color quality. PSoC Express software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature and LED binning compensation. EZ-Color's virtually limitless analog and digital customization allow for simple integration of features in addition to intelligent lighting, such as CapSense, Battery Charging, Image Stabilization, and Motor Control during the development process. These features, along with Cypress' best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications.
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 8% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color device. In USB systems, the IMO will self-tune to 0.25% accuracy for USB communication. EZ-Color GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.

Target Applications

LCD Backlight Large Signs General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights
PrISM (8 to 32 bit) Full-Speed USB (12 Mbps) PWMs (8 to 32 bit) PWMs with Dead band (8 to 24 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Generators (8 to 32 bit)
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 68 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by EZ-Color device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled EZ-Color Device Characteristics.
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Figure 1. Digital System Block Diagram
Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Figure 2. Analog System Block Diagram
All IO (Except Port 7) P0[7] P0[6] P0[4] P0[2] P0[0] AGNDIn RefIn Analog Mux Bus P2[6]
Digital Clocks From Core
To System Bus
To Analog System
P0[5] P0[3] P0[1]
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration 8 8
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
8 8
Row Output Configuration
P2[3]
P2[4] P2[2] P2[0]
P2[1]
GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0]
The Analog System
The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are listed below.

ACI0[1:0]
ACI1[1:0]
Array Input Configuration
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2 and 4 pole band-pass, low-pass, and notch) Amplifiers (up to 2, with selectable gain to 48x) Instrumentation amplifiers (1 with selectable gain to 93x) Comparators (up to 2, with 16 selectable thresholds) DACs (up to 2, with 6- to 9-bit resolution) Multiplying DACs (up to 2, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a PSoC Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible
M8C Interface (Address Bus, Data Bus, Etc.) Interface to Digital System RefHi RefLo AGND ASD20 ASC21 Block Array ACB00 ASC10 ACB01 ASD11
Analog Reference
Reference Generators AGNDIn RefIn Bandgap
Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.
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The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports 0-5. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

Additional System Resources
System Resources, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.
Full-Speed USB (12 Mbps) with 5 configurable endpoints and 256 bytes of RAM. No external components required except two series resistors. Wider than commercial temperature USB operation (-10C to +85C). Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math as well as digital filters. Decimator provides a custom hardware filter for digital signal processing apps. including creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, multi-master are supported. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. Versatile analog multiplexer system.
Track pad, finger sensing. Chip-wide mux that allows analog input from up to 48 IO pins. Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, which can be found under http://www.cypress.com >> DESIGN RESOURCES >> Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1.

EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table Table 1. EZ-Color Device Characteristics
PSoC Part Number CY8CLED04 CY8CLED08 CY8CLED16 CapSense Yes No No LED Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size Flash Size 16K 16K 32K
4 8 16
56 44 64
1 2 4
4 8 16
48 12 12
2 4 4
2 4 4
6 12 12
1K 256 Bytes 2K
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Getting Started
The quickest path to understanding the EZ-Color silicon is by reading this data sheet and using the PSoC Express Integrated Development Environment (IDE). This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest device data sheets on the web at http://www.cypress.com/ez-color.
Development Tools
PSoC Express is a high-level design tool for creating embedded systems using Cypress's PSoC mixed-signal technology. With PSoC Express you create a complete embedded solution including all necessary on-chip peripherals, block configuration, interrupt handling and application software without writing a single line of assembly or C code. PSoC Express solves design problems the way you think about the system:
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click EZ-Color to view a current list of available items.
Select input and output devices based upon system requirements. Add a communications interface and define its interface to system (using registers). Define when and how an output device changes state based upon any and all other system devices.

Based upon the design, automatically select one or more PSoC Mixed-Signal Controllers that match system requirements. Figure 3. PSoC Express
Technical Training Modules
Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.
PSoC Express Subsystems
Express Editor The Express Editor allows you to create designs visually by dragging and dropping inputs, outputs, communication interfaces, and other design elements, and then describing the logic that controls them. Project Manager The Project Manager allows you to work with your applications and projects in PSoC Express. A PSoC Express application is a top level container for projects and their associated files. Each project contains a design that uses a single PSoC device. An application can contain multiple projects so if you are creating an application that uses multiple PSoC devices you can keep all of the projects together in a single application. Most of the files associated with a project are automatically generated by PSoC Express during the build process, but you can make changes directly to the custom.c and custom.h files
Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date as default.
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and also add your own custom code to the project in the Project Manager. Application Editor The Application Editor allows you to edit custom.c and custom.h as well as any C or assembly language source code that you add to your project. With PSoC Express you can create application software without writing a single line of assembly or C code, but you have a full featured application editor at your finger tips if you want it. Build Manager The Build Manager gives you the ability to build the application software, assign pins, and generate the data sheet, schematic, and BOM for your project. Board Monitor The Board Monitor is a debugging tool designed to be used while attached to a prototype board through a communication interface that allows you to monitor changes in the various design elements in real time. It uses The default communication for the board monitor is I the CY3240-I2USB I2C to USB Bridge Debugging/Communication Kit. Tuners A Tuner is a visual interface for the Board Monitor that allows you to view the performance of the HB LED drivers on your test board while your program is running, and manually override values and see the results.
2C.
Document Conventions
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 6 on page 12 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal.
Acronyms Used
The following table lists the acronyms that are used in this document. Table 2. Acronyms
Acronym AC ADC API CPU CT DAC alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor static random access memory Description
Hardware Tools
In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC(R) PWM SC SRAM
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Pin Information
68-Pin Part Pinout
This Section describes, lists, and illustrates the CY8CLED04 EZ-Color device pins and pinout configuration. The CY8CLED04 device is available in the following package. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO. Table 3. 68-Pin Part Pinout (QFN**)
Type Pin No. Digital Analog 1 IO M 2 IO M 3 IO M 4 IO M 5 6 7 Power 8 IO M 9 IO M 10 IO M 11 IO M 12 IO M 13 IO M 14 IO M 15 IO M 16 IO M 17 IO M 18 IO M 19 IO M 20 Power 21 USB 22 USB 23 Power 24 IO 25 IO 26 IO 27 IO 28 IO 29 IO 30 IO 31 IO 32 IO M 33 IO M 34 IO M 35 36 37 38 39 40 41 42 43 44 45 46 IO IO IO IO IO IO IO IO IO M M M M M M M M M
P2[1], M, AI P2[3], M, AI P2[5], M P2[7], M P0[1], M, AI P0[3], M, AIO P0[5], M, AIO P0[7], M, AI Vss Vdd P0[6], M, AI P0[4], M, AI P0[2], M, AI P0[0], M, AI P2[6], M, Ext. VREF P2[4], M, Ext. AGND P2[2], M, AI M, P4[7] M, P4[5] M, P4[3] M, P4[1] NC NC Vss M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] I2C SCL, M, P1[7] I2C SDA, M, P1[5] 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
Name P4[7] P4[5] P4[3] P4[1] NC NC Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] NC NC XRES
Description
68-Pin Device
No connection. No connection. Ground connection.
I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL) ISSP SCLK*. Ground connection.
Supply voltage.
Type Pin No. Digital Analog 50 IO M I2C Serial Data (SDA), ISSP SDATA*. 51 IO I,M 52 IO I,M Optional External Clock Input (EXT53 IO M CLK). 54 IO M 55 IO I,M 56 IO I,M 57 IO I,M 58 IO I,M 59 Power 60 Power 61 IO I,M 62 IO IO,M No connection. No connection. Active high pin reset with internal pull down. 63 64 65 IO IO IO IO,M I,M M
Name P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] P0[1] P2[7]
Input
Document Number: 001-13108 Rev. **
M, P1[3] I2C SCL, M, P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] I2C SDA, M, P1[0] M, P1[2] M, P1[4]
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
QFN
(Top View)
P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES NC NC P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M
Description
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Ground connection. Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2. Analog column mux input and column output. Analog column mux input.
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Table 3. 68-Pin Part Pinout (QFN**) (continued)
47 48 49 IO IO IO M M M P4[0] P4[2] P4[4] 66 67 68 IO IO IO M I,M I,M P2[5] P2[3] P2[1] Direct switched capacitor block input. Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
Register Conventions
This section lists the registers of the CY8CLED04 EZ-Color device.
Abbreviations Used
The register conventions specific to this section are listed in the following table.
Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
Register Mapping Tables
The device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and should not be accessed. Table 4. Register Map Bank 0 Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW EP1_CNT1 EP1_CNT EP2_CNT1 EP2_CNT EP3_CNT1 EP3_CNT EP4_CNT1 EP4_CNT EP0_CR EP0_CNT EP0_DR0 EP0_DR1 Name PMA0_DR PMA1_DR PMA2_DR PMA3_DR PMA4_DR PMA5_DR PMA6_DR PMA7_DR USB_SOF0 USB_SOF1 USB_CR0 USBIO_CR0 USBIO_CR1 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 # RW # RW # RW # RW # # RW RW ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Access RW RW RW RW RW RW RW RW R R RW # RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 # Access is bit specific. RW RW RW RW RW RW RW RW IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR CUR_PP STK_PP Access RW RW RW RW RW RW RW RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 RW RW RW RW # RW # RW RW Access
Blank fields are Reserved and should not be accessed.
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Table 4. Register Map Bank 0 Table: User Space (continued)
Name Addr (0,Hex) 1A 1B PRT7DR PRT7IE PRT7GS PRT7DM2 DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and should not be accessed. RW RW RW RW # W RW # # W RW # # W RW # # W RW # TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access Name EP0_DR2 EP0_DR3 EP0_DR4 EP0_DR5 EP0_DR6 EP0_DR7 AMX_IN AMUXCFG Addr (0,Hex) 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW # # RW Access RW RW RW RW RW RW RW RW Name Addr (0,Hex) 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. DAC_D CPU_SCR1 CPU_SCR0 W W R R RW RW RW RW RW RW RW RW RW RW RW CPU_F Access Name INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 Addr (0,Hex) DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RL Access RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW
Table 5. Register Map Bank 1 Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PMA0_RA PMA1_RA PMA2_RA PMA3_RA Name PMA0_WA PMA1_WA PMA2_WA PMA3_WA PMA4_WA PMA5_WA PMA6_WA PMA7_WA Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 RW RW RW RW RW ASD20CR1 ASD20CR2 ASD20CR3 Access RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Access RW RW RW RW RW RW RW RW EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 RW RW RW RW # # # # Name USBIO_CR2 USB_CR1 Addr (1,Hex) C0 C1 Access RW #
14 PRT5DM0 RW PMA4_RA Blank fields are Reserved and should not be accessed.
ASC21CR0 94 # Access is bit specific.
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Table 5. Register Map Bank 1 Table: Configuration Space (continued)
Name PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 15 16 17 18 19 1A 1B PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and should not be accessed. RW RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 RW RW RW RW RW RW RW RW RW RW RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 Access RW RW RW Name PMA5_RA PMA6_RA PMA7_RA Addr (1,Hex) 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW RW RW RW RW Access RW RW RW Name ASC21CR1 ASC21CR2 ASC21CR3 Addr (1,Hex) 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. DAC_CR CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW CPU_F IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP Access RW RW RW MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 Name Addr (1,Hex) D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RL W W RW W RW RW RW RW RW RW RW RW RW R RW RW RW RW Access
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CY8CLED04
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED04 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. Figure 4. Voltage versus CPU Frequency
5.25
The following table lists the units of measure that are used in this chapter. Table 6. Units of Measure
Symbol
o
Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps V
Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
C
dB fF Hz KB Kbit kHz k
4.75 Vdd Voltage
MHz M A F H s V Vrms
lid ng Va rati n e io Op Reg
3.00
93 kHz CPU Frequency
12 MHz
24 MHz
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Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Symbol TSTG Storage Temperature Description Min -55 25 Typ Max +100
o
Units C
Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability.
TA Vdd VIO VIO2 IMIO IMAIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current
-40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 -
- - - - - - - -
+85 +6.0
o
C
V
Vdd + 0.5 V Vdd + 0.5 V +50 +50 - 200 mA mA V mA Human Body Model ESD.
Operating Temperature
Table 8. Operating Temperature
Symbol TA TAUSB TJ Ambient Temperature Ambient Temperature using USB Junction Temperature Description Min -40 -10 -40 - - - Typ Max +85 +85 +100 Units
oC o
Notes
C The temperature rise from ambient to junction is package specific. See "Thermal Impedance" on page 30. The user must limit the power consumption to comply with this requirement.
oC
DC Electrical Characteristics
DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 9. DC Chip-Level Specifications
Symbol Vdd IDD5 Supply Voltage Supply Current, IMO = 24 MHz (5V) Description Min 3.0 - - 14 Typ Max 5.25 27 V mA Units Notes See DC POR and LVD specifications, Table 20 on page 20. Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC, analog power = off.
IDD3
Supply Current, IMO = 24 MHz (3.3V)
-
8
14
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a
-
3
6.5
A
ISBH
-
4
25
A
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled.
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CY8CLED04
DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 10. DC GPIO Specifications
Symbol RPU RPD VOH Pull-Up Resistor Pull-Down Resistor High Output Level Description 4 4 Vdd - 1.0 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 200 mA maximum combined IOL budget. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes
VOL
Low Output Level
-
-
0.75
V
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.1 - - - -
- - 60 1 3.5 3.5
0.8
V V
- - 10 10
mV nA pF pF
DC Full-Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10C TA 85C, or 3.0V to 3.6V and -10C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 11. DC Full-Speed (12 Mbps) USB Specifications
Symbol USB Interface VDI VCM VSE CIN IIO REXT VUOH VUOHI VUOL ZO VCRS Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance High-Z State Data Line Leakage External USB Series Resistor Static Output High, Driven Static Output High, Idle Static Output Low USB Driver Output Impedance D+/D- Crossover Voltage 0.2 0.8 0.8 - -10 23 2.8 2.7 - 28 1.3 - - - - - - - - - - - - 2.5 2.0 20 10 25 3.6 3.6 0.3 44 2.0 V V V pF A V V V V 0V < VIN < 3.3V. In series with each USB pin. 15 k 5% to Ground. Internal pull-up enabled. 15 k 5% to Ground. Internal pull-up enabled. 15 k 5% to Ground. Internal pull-up enabled. Including REXT Resistor. | (D+) - (D-) | Description Min Typ Max Units Notes
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DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 12. 5V DC Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) - - - - - - 0.0 0.5 1.6 1.3 1.2 7.0 20 4.5 - - 10 8 7.5 35.0 - 9.5 Vdd Vdd - 0.5 mV mV mV V/oC pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Min Typ Max Units Notes
GOLOA
Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 - - - - - - - - - 65
-
-
dB
VOHIGHOA
High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High - - - - - - 400 500 800 1200 2400 4600 80 - - - 0.2 0.2 0.5 800 900 1000 1600 3200 6400 - V V V V V V A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
VOLOWOA
Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High
ISOA
Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High
PSRROA
Supply Voltage Rejection Ratio
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Table 13. 3.3V DC Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range - - - 0.2 7.0 20 4.5 - 35.0 - 9.5 Vdd - 0.2 V/oC pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. - - 1.65 1.32 10 8 mV mV Min Typ Max Units Notes
GOLOA
Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 65
-
-
dB
VOHIGHOA
High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only - - - - - - 400 500 800 1200 2400 4600 80 - - - 0.2 0.2 0.2 800 900 1000 1600 3200 6400 - V V V V V V A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
VOLOWOA
Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low
ISOA
Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High
PSRROA
Supply Voltage Rejection Ratio
DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 14. DC Low Power Comparator Specifications
Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low power comparator (LPC) reference voltage range - - Min 0.2 - 10 2.5 Typ 40 30 Max Vdd - 1 V A mV Units Notes
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DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 15. 5V DC Analog Output Buffer Specifications
Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High - - 0.5 x Vdd + 1.1 0.5 x Vdd + 1.1 VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - 53 1.1 2.6 64 5.1 8.8 - mA mA dB (0.5 x Vdd - 1.3) VOUT (Vdd - 2.3). V V 0.6 0.6 - - - - - - V V - - 0.5 Min 3 +6 - Typ 12 - Vdd - 1.0 Max Units mV V/C V Notes
Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 VOLOWOB Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - 34 0.8 2.0 64 2.0 4.3 - mA mA dB (0.5 x Vdd - 1.0) VOUT (0.5 x Vdd + 0.9). V V - - - - V V - - 1 1 - - - - 0.5 Min 3 +6 Typ 12 - Vdd - 1.0 Max Units mV V/C V Notes
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DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 17. 5V DC Analog Reference Specifications
Symbol BG - - - - - - - AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = Vdd/2)a AGND = BandGapa AGND = 1.6 x BandGapa AGND Block to Block Variation (AGND = Vdd/2)a RefHi = Vdd/2 + BandGap Description Bandgap Voltage Reference Min 1.28 Vdd/2 0.04 2 x BG 0.048 P2[4] 0.011 BG 0.009 1.6 x BG - 0.022 -0.034 Typ 1.30 Vdd/2 0.01 2 x BG 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000 Max 1.32 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.016 1.6 x BG + 0.018 0.034 V V V V V V V V Units
Vdd/2 +
Vdd/2 +
Vdd/2 +
BG + 0.10 3 x BG + 0.06 2 x BG + P2[6] + 0.077 P2[4] + BG + 0.098 P2[4] + P2[6]+ 0.100 3.2 x BG + 0.076
BG - 0.10 BG - - RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 3 x BG 0.06 2 x BG + P2[6] 0.113 P2[4] + BG 0.130 P2[4] + P2[6] 0.133 3.2 x BG - 0.112 3 x BG 2 x BG + P2[6] 0.018 P2[4] + BG 0.016 P2[4] + P2[6] 0.016 3.2 x BG
V V
-
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
V
-
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
V
- -
RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap
V V
Vdd/2 -
Vdd/2 -
Vdd/2 BG + 0.04 BG + 0.06 2 x BG P2[6] + 0.134 P2[4] BG + 0.107 P2[4] P2[6] + 0.110
BG - 0.04 BG + 0.024 - - RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) BG - 0.06 BG 2 x BG P2[6] 0.084 P2[4] BG 0.056 P2[4] P2[6] 0.057 2 x BG P2[6] + 0.025 P2[4] BG + 0.026 P2[4] P2[6] + 0.026
V V
-
RefLo = P2[4] - BandGap (P2[4] = Vdd/2)
V
-
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V.
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Table 18. 3.3V DC Analog Reference Specifications
Symbol BG - - - - - - - - - - - AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGapa AGND = 1.6 x BandGapa AGND Column to Column Variation (AGND = Vdd/2)a RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Description Bandgap Voltage Reference Min 1.28 Vdd/2 0.03 Typ 1.30 Vdd/2 0.01 Max 1.32 Vdd/2 + 0.005 V V Units Notes
Not Allowed P2[4] 0.008 BG 0.009 1.6 x BG - 0.027 -0.034 P2[4] + 0.001 BG + 0.005 1.6 x BG - 0.010 0.000 P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034 V V V V
Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.075 P2[4] + P2[6] 0.009 P2[4] + P2[6] + 0.057 V
- - - - - -
RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] P2[6] 0.048 P2[4]P2[6] + 0.022 P2[4] P2[6] + 0.092 V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V.
DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 19. DC Analog PSoC Block Specifications
Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor) - - Min 80 Typ 12.2 - - Max fF Units k Notes
DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only.
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Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. Table 20. DC POR and LVD Specifications
Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 V V V V V V V V V - - - 92 0 0 - - - mV mV mV - 2.82 4.39 4.55 - V V V - Description Vdd Value for PPOR Trip (positive ramp) 2.91 4.39 4.55 - V V V Min Typ Max Units Notes
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 21. DC Programming Specifications
Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a - - 2.1 - - - Vdd - 1.0 50,000 1,800,00 0 10 Min 15 - - - - - - - - - Typ 30 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Max V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull-down resistor. Driving internal pull-down resistor. Units mA Notes
Flash Data Retention
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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AC Electrical Characteristics
AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 22. AC Chip-Level Specifications
Symbol FIMO245V FIMO243V FIMOUSB5V FIMOUSB3V FCPU1 FCPU2 FBLK5 FBLK3 F32K1 Jitter32k Step24M Fout48M Jitter24M1 FMAX TRAMP Description Internal Main Oscillator Frequency for 24 MHz (5V) Internal Main Oscillator Frequency for 24 MHz (3.3V) Internal Main Oscillator Frequency with USB (5V) Frequency locking enabled and USB traffic present. Internal Main Oscillator Frequency with USB (3.3V) Frequency locking enabled and USB traffic present. CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency (5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Peak-to-Peak Supply Ramp Time Min 23.04 22.08 23.94 23.94 0.93 0.93 0 0 15 - - 46.08 - 0 24 24 24 24 24 12 48 24 32 100 50 48.0 300 - - 12.96 - - 49.92
a,c
Typ
Max 24.96a,b 25.92b,c 24.06b 24.06b 24.96a,b 12.96b,c 49.92 64
a,b,d
Units MHz MHz MHz MHz MHz MHz MHz MHz kHz ns kHz MHz ps MHz s
Notes Trimmed for 5V operation using factory trim values. Trimmed for 3.3V operation using factory trim values. -10C TA 85C 4.35 Vdd 5.15 -0C TA 70C 3.15 Vdd 3.45
Refer to the AC Digital Block Specifications.
25.92b, d
Trimmed. Utilizing factory trim values.
Maximum frequency of signal on row input or row output. -
a. b. c. d.
4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules.
Figure 5. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 23. AC GPIO Specifications
Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 Min - - - 27 22 Typ 12 18 18 - - Max Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%
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Figure 6. GPIO Timing Diagram
90% G PIO Pin O utput Voltage 10%
TRiseF TRiseS
TFallF TFallS
AC Full-Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10C TA 85C, or 3.0V to 3.6V and -10C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 24. AC Full-Speed (12 Mbps) USB Specifications
Symbol TRFS TFSS TRFMFS Transition Rise Time Transition Fall Time Rise/Fall Time Matching: (TR/TF) Description 4 4 90 12 0.25% Min - - - 12 Typ 20 20 111 12 + 0.25% Max Units ns ns % Mbps For 50 pF load. For 50 pF load. For 50 pF load. Notes
TDRATEFS Full-Speed Data Rate
AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 25. 5V AC Operational Amplifier Specifications
Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High 0.01 0.5 4.0 - - - - - - V/s V/s V/s 0.15 1.7 6.5 - - - - - - V/s V/s V/s - - - - - - 5.9 0.92 0.72 s s s - - - - - - 3.9 0.72 0.62 s s s Min Typ Max Units Notes
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Table 25. 5V AC Operational Amplifier Specifications (continued)
Symbol BWOA Description Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.75 3.1 5.4 - - - - 100 - - - - MHz MHz MHz nV/rt-Hz Min Typ Max Units Notes
Table 26. 3.3V AC Operational Amplifier Specifications
Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz 0.24 1.8 - - - - V/s V/s 0.31 2.7 - - - - V/s V/s - - - - 5.41 0.72 s s - - - - 3.92 0.72 s s Min Typ Max Units Notes
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 7. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
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At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 8. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 27. AC Low Power Comparator Specifications
Symbol TRLPC LPC response time Description - Min - Typ 50 Max Units s Notes 50 mV overdrive comparator reference set within VREFLPC.
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AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 28. AC Digital Block Specifications
Function Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50
a
Description
Min 50a - - 50a - - - - - - - -
Typ -
Max
Units ns MHz MHz ns MHz MHz
Notes
49.92 25.92 - 49.92 25.92
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
- - - - - - - - - - -
- - - 49.92 49.92 24.6 8.2 4.1 - 24.6 24.6
ns ns ns MHz MHz MHz MHz MHz ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
50a - - - - - 50a - -
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 29. AC External Clock Specifications
Symbol FOSCEXT - - Description Frequency for USB Applications Duty Cycle Power up to IMO Switch Min 23.94 47 150 24 50 - Typ Max 24.06 53 - Units MHz % s Notes
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AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 30. 5V AC Analog Output Buffer Specifications
Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.65 0.65 - - - - V/s V/s 0.65 0.65 - - - - V/s V/s - - - - 2.2 2.2 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 2.5 2.5 s s Min Typ Max Units Notes
Table 31. 3.3V AC Analog Output Buffer Specifications
Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 - - - - kHz kHz 0.7 0.7 - - - - MHz MHz 0.5 0.5 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s - - - - 2.6 2.6 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 3.8 3.8 s s Min Typ Max Units Notes
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AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 32. AC Programming Specifications
Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - - Min - - - - - 10 30 - - Typ 20 20 - - 8 - - 45 50 Max Units ns ns ns ns MHz ms ms ns ns Vdd > 3.6 3.0 Vdd 3.6 Notes
AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 33. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Description 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0
a
Fast Mode Min - - - - - - - - 50 Max 400 Units kHz s s s s s ns s s ns Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
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Packaging Information
Packaging Dimensions
This section illustrates the package specification for the CY8CLED04 EZ-Color device, along with the thermal impedance for the package and solder reflow peak temperatures. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 10. 68-Lead (8x8 mm x 0.89 mm) QFN
51-85214 *C
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
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Thermal Impedance
Table 34. Thermal Impedance for the Package
Package 68 QFN** * TJ = TA + POWER x JA Typical JA * 13.05 oC/W
** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Table 35. Solder Reflow Peak Temperature
Package 68 QFN Minimum Peak Temperature* 240oC Maximum Peak Temperature 260oC
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store. CY3261A-RGB EZ-Color RGB Kit The CY3261A-RGB board is a preprogrammed HB LED color mix board with seven pre-set colors using the CY8CLED16 EZ-Color HB LED Controller. The board is accompanied by a CD containing the color selector software application, PSoC Express 3.0 Beta 2, PSoC Programmer, and a suite of documents, schematics, and firmware examples. The color selector software application can be installed on a host PC and is used to control the EZ-Color HB LED controller using the included USB cable. The application enables you to select colors via a CIE 1931 chart or by entering coordinates. The kit includes:

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Development Tools
Software
This section presents the development tools available for all current PSoC device families including the CY8CLED04 EZ-Color. PSoC ExpressTM As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress. PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers.
Training Board (CY8CLED16) One mini-A to mini-B USB Cable PSoC Express CD-ROM Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Express 3.0 you must use a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
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CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

USB 2.0 Cable
Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
3rd-Party Tools Device Programmers
All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board - AN2323" at http://www.cypress.com/an2323. The following table lists the CY8CLED04 EZ-Color device key package features and ordering codes.
Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide
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Ordering Information
Key Device Features
Table 36. Device Key Features and Ordering Information
Analog Outputs Analog Blocks Digital IO Pins Analog Inputs Digital Blocks Temperature Range
68 Pin (8x8 mm) QFN 68 Pin (8x8 mm) QFN (Tape and Reel)
CY8CLED04-68LFXI CY8CLED04-68LFXIT
16K 16K
1K 1K
-40C to +85C -40C to +85C
4 4
6 6
56 56
48 48
2 2
Yes Yes
Ordering Code Definitions
CY 8 C LED xx - xx xxxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count Part Number LED Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress
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XRES Pin
Ordering Code
Package
Flash (Bytes)
SRAM (Bytes)
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Revision History
Table 37. CY8CLED04 Data Sheet Revision History
Document Title: CY8CLED04 EZ-Color HB LED Controller Document Number: 001-13108 Revision ** ECN # 1148504 Issue Date See ECN Origin of Change SFVTMP3 New document (revision **). Description of Change
Distribution: External/Public
Posting: None
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13108 Rev. **
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